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1 rad-hard, 5.0v/3.3v -processor supervisory circuits isl705aeh, isl705beh, isl705ceh, isl706aeh, isl706beh, isl706ceh this family of devices are radiation hardened 5.0v/3.3v supervisory circuits that reduce the complexity required to monitor supply voltages in microprocessor systems. these devices significantly improve accuracy and reliability relative to discrete solutions. each ic provides four key functions. 1. a reset output during power-up, power-down, and brownout conditions. 2. an independent watchdog output that goes low if the watchdog input has not been toggled within 1.6s. 3. a precision threshold detector for monitoring a power supply other than v dd . 4. an active-low manual-reset input. specifications for rad hard qml devices are controlled by the defense logistics agency land and maritime (dla). the smd numbers listed in the ?orderin g information? table on page 3 must be used when ordering. detailed electrical specifications for the isl705aeh, isl705beh, isl705ceh, isl706aeh, isl706beh and isl706ceh are contained in smd 5962-11213 . a ?hot-link? is also provided on our website for downloading . applications ? supervisor for -processors, -controllers, fpgas and dsps ? critical power supply monitoring ? reliable replacement of discrete solutions features ? electrically screened to smd 5962-11213 ? qml qualified per mil-prf-38535 requirements ?radiation hardness - high dose rate. . . . . . . . . . . . . . . . . . . . . . . . . . 100krad(si) - low dose rate . . . . . . . . . . . . . . . . . . . 100krad(si) (note 1) - sel/seb let th . . . . . . . . . . . . . . . . . . . . 86mev * cm 2 /mg ? precision supply voltage monitor - 4.65v threshold in the isl705aeh/beh/ceh - 3.08v threshold in the isl706aeh/beh/ceh ? 200ms (typ) reset pulse width - active high, active low and open drain options ? independent watchdog timer with 1.6s (typ) timeout ? precision threshold detector - 1.25v threshold in the isl705aeh/beh/ceh - 0.6v threshold in the isl706aeh/beh/ceh ? debounced ttl/cmos compatible manual-reset input ? reset output valid at v dd = 1.2v related literature ? an1650 , ?isl705xrh evaluation board user?s guide? ? an1671 , ?isl706xrh evaluation board user?s guide? ? an1651 , ?single event effects (see) testing of the isl705xrh/eh and isl706xrh/eh rad hard supervisory circuits? note: 1. product capability established by initial ch aracterization. the eh version is acceptance tested on a wafer by wafer basis to 50krad(si) at low dose rate. 1 2 3 4 8 7 6 5 mr v dd gnd pfi wdo rst wdi pfo p 165k 49.9k isl705aeh 5v supervisor application with overvoltage protection nmi rst i/o v cc 5v power supply figure 1. typical application 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 25 50 75 100 125 150 figure 2. precision threshold detector low dose ionizing characteristic curve krad (si) v pfi (v) isl705xeh isl706xeh march 30, 2012 fn8262.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl705aeh, isl705beh, isl705ceh, isl706aeh, isl706beh, isl706ceh 2 fn8262.0 march 30, 2012 pin configurations isl705aeh, isl706aeh (8 ld flatpack) top view isl705beh, isl706beh (8 ld flatpack) top view isl705ceh, isl706ceh (8 ld flatpack) top view 1 2 3 4 8 7 6 5 v dd gnd pfi wdo rst wdi pfo mr 1 2 3 4 8 7 6 5 v dd gnd pfi wdo rst wdi pfo mr 1 2 3 4 8 7 6 5 v dd gnd pfi wdo rst_od wdi pfo mr pin descriptions isl705aeh isl706aeh isl705beh isl706beh isl705ceh isl706ceh name description 111mr manual reset. mr is an active-low, debounced, tt l/cmos compatible input that may be used to trigger a reset pulse. 222v dd power supply. v dd is a supply voltage input that provides power to all internal circuitry. this input is also monitored and used to trigger a reset pulse. reset is guaranteed operable after v dd rises above 1.2v. 333gnd ground. gnd is a supply voltage return for all internal circuitry. this return establishes the reference level for voltage detection and should be connected to signal ground. 444pfi power fail input . pfi is an input to a threshold detector, which may be used to monitor another supply voltage level. the threshold of the detector (v pfi ) is 1.25v in the isl705aeh/beh/ceh and 0.6v in the isl706aeh/beh/ceh. 555pfo power fail output. pfo is an active-low, push-pull outp ut of a threshold detector that indicates the voltage at the pfi pin is less than v pfi . 666wdi watchdog input. wdi is a tri-state input that monito rs microprocessor activity. if the microprocessor does not toggle wdi within 1.6s and wdi is not tri-stated, wdo goes low. as long as reset is asserted or wdi is tri-stated, the watchdog timer will stay cleared and will not count. as soon as reset is released and wdi is driven high or low, the timer will start counting. floating wdi or connecting wdi to a high impedance tri-state buffer disables the watchdog feature. 7--rst reset . rst is an active-low, push-pull output th at is guaranteed to be low once v dd reaches 1.2v. as v dd rises, rst stays low. when v dd rises above a 4.65v (isl705aeh/beh/ceh) or 3.08v (isl706aeh/beh /ceh) reset threshold, an internal timer releases rst after about 200ms. rst pulses low whenever v dd goes below the reset threshold. if a brownout condition occurs in the middle of a previously initiated reset pulse, the pulse will continue fo r at least 140ms. on power-down, once v dd falls below the reset threshold, rst goes low and is guaranteed low until v dd drops below 1.2v. -7-rst reset. rst is an active-high, push-pull output. rst is the inverse of rst . --7rst_od reset. rst_od is an active-low, open-drain output that goes low when reset is asserted. this pin may be pulled up to v dd with a resistor consistent with the sink and leakage current specifications of the output. behavior is otherwise identical to the rst pin. 888wdo watchdog output. wdo is an active-low, push-pull output that goes low if the microprocessor does not toggle wdi within 1.6s and wdi is not tri-stated. wdo is usually connected to the non-maskable inte rrupt input of a microprocessor. when v dd drops below the reset threshold, wdo will go low whether or not the watchdog timer has timed out. reset is simultaneously asse rted, thus preventing an interrupt. since floating wdi disables the internal timer, wdo goes low only when v dd drops below the reset threshold, thus functioning as a low line output.
isl705aeh, isl705beh, isl705ceh, isl706aeh, isl706beh, isl706ceh 3 fn8262.0 march 30, 2012 ordering information ordering number part number temp range (c) package (rohs compliant) pkg. dwg. # 5962r1121307vxc isl705aehvf (note 2) -55 to +125 8 ld flatpack k8.a 5962r1121307v9a isl705aehvx -55 to +125 die isl705arhf/proto isl705arhf/proto (note 2) -55 to +125 8 ld flatpack k8.a isl705arhx/sample isl705arhx/sample -55 to +125 die 5962r1121308vxc isl705behvf (note 2) -55 to +125 8 ld flatpack k8.a 5962r1121308v9a isl705behvx -55 to +125 die isl705brhf/proto isl705brhf/proto (note 2) -55 to +125 8 ld flatpack k8.a isl705brhx/sample isl705brhx/sample -55 to +125 die 5962r1121309vxc isl705cehvf (note 2) -55 to +125 8 ld flatpack k8.a 5962r1121309v9a isl705cehvx -55 to +125 die isl705crhf/proto isl705crhf/proto (note 2) -55 to +125 8 ld flatpack k8.a isl705crhx/sample isl705crhx/sample -55 to +125 die 5962r1121310vxc isl706aehvf (note 2) -55 to +125 8 ld flatpack k8.a 5962R1121310V9A isl706aehvx -55 to +125 die isl706arhf/proto isl706arhf/proto (note 2) -55 to +125 8 ld flatpack k8.a isl706arhx/sample isl706arhx/sample -55 to +125 die 5962r1121311vxc isl706behvf (note 2) -55 to +125 8 ld flatpack k8.a 5962r1121311v9a isl706behvx -55 to +125 die isl706brhf/proto isl706brhf/proto (note 2) -55 to +125 8 ld flatpack k8.a isl706brhx/sample isl706brhx/sample -55 to +125 die 5962r1121312vxc isl706cehvf (note 2) -55 to +125 8 ld flatpack k8.a 5962r1121312v9a isl706cehvx -55 to +125 die isl706crhf/proto isl706crhf/proto (note 2) -55 to +125 8 ld flatpack k8.a isl706crhx/sample isl706crhx/sample -55 to +125 die isl705xrheval1z isl705xrh evaluation board isl706xrheval1z isl706xrh evaluation board note: 2. these intersil pb-free hermetic packaged prod ucts employ 100% au plate - e4 termin ation finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations.
isl705aeh, isl705beh, isl705ceh, isl706aeh, isl706beh, isl706ceh 4 fn8262.0 march 30, 2012 functional block diagrams timing diagrams + v ref v dd por gnd wdt v ref pfi wdi pb wdo pf pfo mr rst isl705aeh, isl706aeh v ref v dd por gnd wdt v ref pfi wdi pb wdo pf pfo mr rst isl705beh, isl706beh isl705ceh, isl706ceh v ref v dd por gnd wdt v ref pfi wdi pb wdo pf pfo mr rst_od - + - + - + - + - + - figure 3. rst, rst , mr and wdo timing diagram figure 4. watchdog timing diagram v dd mr rst t rst v rst 1.2v t rst t rst >t mr rst t wp < t wd < t wd < t wd t rst rst t rst t wd
isl705aeh, isl705beh, isl705ceh, isl706aeh, isl706beh, isl706ceh 5 fn8262.0 march 30, 2012 absolute maximum rating s thermal information supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v voltage on all other inputs . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd + 0.3v esd rating human body model (tested per mil-prf-883 3015.7). . . . . . . . . .3.0kv machine model (tested per jesd22-a115c) . . . . . . . . . . . . . . . . . . 300v charged device model (tested per jesd22-c110d) . . . . . . . . . . . .1.0kv latch up (tested per jesd-78c) . . . . . . . . . . . . . . . . . . . . . . class 2, level a thermal resistance (typical) ja (c/w) jc (c/w) 8 ld flatpack package (notes 3, 4). . . . . . 140 15 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c recommended operating conditions temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55c to +125c supply voltage isl705aeh/beh/ceh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75v to 5.5v isl706aeh/beh/ceh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.15v to 3.6v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 3. ja is measured with the component mounted on a low effective thermal conductivity test board in free air. see tech brief tb379 for details. 4. for jc , the ?case temp? location is the center of the package underside. electrical specifications unless otherwise specified v dd = 4.75v to 5.5v for the isl705aeh/beh/ceh, v dd = 3.15v to 3.6v for the isl706aeh/beh/ceh t a = -55c to +125c. boldface limits apply over the operating temperature rang e, -55c to +125c; over a total ionizing dose of 100krad(si) with exposure at a high dose ra te of 50 - 300krad(si)/s; and over a total ionizing dose of 50kr ad(si) with exposure at a low dose rate of <10mrad(si)/s. symbol parameter conditions min (note 5) typ (note 6) max (note 5) units power supply section v dd operating supply voltage (note 7) isl705aeh/beh/ceh 1.2 5 5.5 v isl706aeh/beh/ceh 1.2 3.3 3.6 v i dd operating supply current isl705aeh/beh/ceh 530 a isl706aeh/beh/ceh 400 a reset section v rst reset threshold voltage isl705aeh/beh/ceh 4.50 4.65 4.75 v isl706aeh/beh/ceh 3.00 3.08 3.15 v v hys reset threshold voltage hysteresis isl705aeh/beh/ceh 20 40 mv isl706aeh/beh/ceh 20 30 mv t rst reset pulse width 140 200 280 ms v out reset output voltage isl705aeh/beh, i source = 800a v dd - 1.5 v isl705aeh/beh/ceh, i sink = 3.2ma 0.4 v isl706aeh/beh, i source = 500a 0.8 x v dd v isl706aeh/beh/ceh, i sink = 1.2ma 0.3 v isl70xaeh/ceh, v dd = 1.2v, i sink = 100a 0.3 v isl70xbeh, v dd = 1.2v, i source = 4a 0.9 v i leak reset output leakage current isl705ceh, v out = v dd 1 a isl706ceh, v out = v dd 1 a
isl705aeh, isl705beh, isl705ceh, isl706aeh, isl706beh, isl706ceh 6 fn8262.0 march 30, 2012 watchdog section t wd watchdog time-out period 1.00 1.60 2.25 s t wp watchdog input (wdi) pulse width isl705aeh/beh/ceh, v il =0.4v, v ih = 0.8 x v dd 50 ns isl706aeh/beh/ceh, v il =0.4v, v ih = 0.8 x v dd 100 ns v il watchdog input (wdi) threshold voltage isl705aeh/beh/ceh 0.8 v v ih isl705aeh/beh/ceh 3.5 v v il isl706aeh/beh/ceh 0.6 v v ih isl706aeh/beh/ceh 0.7 x v dd v i wdi watchdog input (wdi) current isl705aeh/beh/ceh, wdi = v dd 100 a isl705aeh/beh/ceh, wdi = 0v -100 a isl706aeh/beh/ceh, wdi = v dd 5 a isl706aeh/beh/ceh, wdi = 0v -5 a v wdo watchdog output (wdo ) voltage isl705aeh/beh/ceh, i source = 800a v dd - 1.5 v isl705aeh/beh/ceh, i sink = 1.2ma 0.4 v isl706aeh/beh/ceh, i source = 500a 0.8 x v dd v isl706aeh/beh/ceh, i sink = 500a 0.3 v manual reset section i mr manual reset (mr ) pull-up current isl705aeh/beh/ceh, mr =0v -500 -100 a isl706aeh/beh/ceh, mr =0v -250 -25 a t mr manual reset (mr ) pulse width isl705aeh/beh/ceh 150 ns isl706aeh/beh/ceh 150 ns v il manual reset (mr ) input threshold voltage isl705aeh/beh/ceh 0.8 v v ih 2.0 v v il isl706aeh/beh/ceh 0.6 v v ih 0.7 x v dd v t md manual reset (mr ) to reset out delay isl705aeh/beh/ceh 100 ns isl706aeh/beh/ceh 100 ns threshold detector section v pfi power fail input (pfi) input threshold voltage isl705aeh/beh/ceh 1.20 1.25 1.30 v isl706aeh/beh/ceh 0.576 0.6 0.624 v i pfi power fail input (pfi) input current -10 10 na v pfo power fail output (pfo) output voltage isl705aeh/beh/ceh, i source = 800a v dd - 1.5 v isl705aeh/beh/ceh, i sink = 3.2ma 0.4 v isl706aeh/beh/ceh, i source = 500a 0.8 x v dd v isl706aeh/beh/ceh, i sink = 1.2ma 0.3 v t rpfi pfi rising threshold crossing to pfo delay isl705aeh/beh/ceh 7 15 s isl706aeh/beh/ceh 11 20 s electrical specifications unless otherwise specified v dd = 4.75v to 5.5v for the isl705aeh/beh/ceh, v dd = 3.15v to 3.6v for the isl706aeh/beh/ceh t a = -55c to +125c. boldface limits apply over the operating temperature rang e, -55c to +125c; over a total ionizing dose of 100krad(si) with exposure at a high dose ra te of 50 - 300krad(si)/s; and over a total ionizing dose of 50kr ad(si) with exposure at a low dose rate of <10mrad(si)/s. (continued) symbol parameter conditions min (note 5) typ (note 6) max (note 5) units
isl705aeh, isl705beh, isl705ceh, isl706aeh, isl706beh, isl706ceh 7 fn8262.0 march 30, 2012 t fpfi pfi falling threshold crossing to pfo delay isl705aeh/beh/ceh 20 35 s isl706aeh/beh/ceh 25 40 s notes: 5. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. 6. typical values shown reflect t a = t j = +25c operation and are not guaranteed. 7. reset is the only parameter operable within 1.2v and the minimum recommended operating supply voltage. typical performance curves figure 5. i dd vs temperature figure 6. v rst vs temperature figure 7. v pfi vs temperature figure 8. isl705xeh reset and reset assertion electrical specifications unless otherwise specified v dd = 4.75v to 5.5v for the isl705aeh/beh/ceh, v dd = 3.15v to 3.6v for the isl706aeh/beh/ceh t a = -55c to +125c. boldface limits apply over the operating temperature rang e, -55c to +125c; over a total ionizing dose of 100krad(si) with exposure at a high dose ra te of 50 - 300krad(si)/s; and over a total ionizing dose of 50kr ad(si) with exposure at a low dose rate of <10mrad(si)/s. (continued) symbol parameter conditions min (note 5) typ (note 6) max (note 5) units 200 250 300 350 400 450 500 550 -80-60-40-200 20406080100120140 temperature (c) i dd (a) isl705xeh isl706xeh 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -80 -60 -40 -20 0 20 40 60 80 100 120 140 v rst (v) temperature (c) isl705xeh isl706xeh 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 -80 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (c) v pfi (v) isl705xeh isl706xeh vdd rst rst
isl705aeh, isl705beh, isl705ceh, isl706aeh, isl706beh, isl706ceh 8 fn8262.0 march 30, 2012 figure 9. isl706xeh reset and reset assertion figure 10. isl705xeh reset and reset deassertion figure 11. isl706xeh reset and reset deassertion figure 12. isl705xeh pfi to pfo response figure 13. isl706xeh pfi to pfo response typical performance curves (continued) vdd rst rst vdd rst rst vdd rst rst pfo pfi pfo pfi
isl705aeh, isl705beh, isl705ceh, isl706aeh, isl706beh, isl706ceh 9 fn8262.0 march 30, 2012 post radiation characteristics unless otherwise specified, v dd = 4.75v to 5.5v for the isl705aeh/beh/ceh, v dd = 3.15v to 3.6v for the isl706aeh/beh/ceh t a = +25c. this data is parameter deltas post radiation exposure at a rate of 50 to 300rad(si)/s. this data is intended to show typical parameter shifts due to high dose rate radiation. these are not limits nor are they guaranteed. symbol parameter conditions 0 - 25krad 0 - 50krad 0 - 75krad 0 - 100krad units power supply section i dd operating supply current isl705aeh/beh/ceh -2 -2.44 -3.86 -4.88 a isl706aeh/beh/ceh -4.79 -7.47 -6.93 -8.88 a reset section v rst reset threshold voltage isl705aeh/beh/ceh -8.1 -13.1 -17.5 -18.1 mv isl706aeh/beh/ceh -1 -3.25 -5.38 -7.25 mv v hys reset threshold voltage hysteresis isl705aeh/beh/ceh -3.75 -1.9 -5 -3.12 mv isl706aeh/beh/ceh 0.375 0.25 0.625 0.625 mv t rst reset pulse width -2.13 -2.18 -2.39 -2.35 ms watchdog section t wd watchdog time-out period -56 -72 -81 -80 ms manual reset section t md manual reset (mr ) to reset out delay isl705aeh/beh/ceh 0.028 0.146 0.274 0.368 ns isl706aeh/beh/ceh 0.305 0.605 0.793 0.956 ns threshold detector section v pfi power fail input (pfi) input threshold voltage isl705aeh/beh/ceh 0.94 0.31 0 -0.62 mv isl706aeh/beh/ceh -1.56 -2.5 -2.5 -2.5 mv t rpfi pfi rising threshold crossing to pfo delay isl705aeh/beh/ceh -0.026 -0.047 -0.085 -0.068 s isl706aeh/beh/ceh 0.028 -0.058 0.11 -0.11 s t fpfi pfi falling threshold crossing to pfo delay isl705aeh/beh/ceh -0.397 -0.77 -1.17 -2.88 s isl706aeh/beh/ceh -0.35 -0.782 -1.516 -2.087 s post radiation characteristics unless otherwise specified, v dd = 4.75v to 5.5v for the isl705aeh/beh/ceh, v dd = 3.15v to 3.6v for the isl706aeh/beh/ceh t a = +25c. this data is typical mean test data post radiation exposure at a rate of <10mrad(si)/s. this data is intended to show typical parameter shifts due to low dose rate radiation. these are not limits nor are they guaranteed figure 14. isl705xeh i dd vs low dose rate radiation figure 15. isl705xeh v rst vs low dose rate radiation krad(si) i dd (a) 450 460 470 480 490 500 510 520 530 540 0 255075100125150 biased grounded v rst (v) krad(si) 4.45 4.50 4.55 4.60 4.65 4.70 4.75 4.80 0 25 50 75 100 125 150 biased grounded
isl705aeh, isl705beh, isl705ceh, isl706aeh, isl706beh, isl706ceh 10 fn8262.0 march 30, 2012 figure 16. isl705xeh v hys vs low dose rate radiation figure 17. isl705xeh t rst vs low dose rate radiation figure 18. isl705xeh t wd vs low dose rate radiation figure 19. isl705xeh t md vs low dose rate radiation figure 20. isl705xeh v pfi vs low dose rate radiation figure 21. isl705xeh t rpfi vs low dose rate radiation post radiation characteristics unless otherwise specified, v dd = 4.75v to 5.5v for the isl705aeh/beh/ceh, v dd = 3.15v to 3.6v for the isl706aeh/beh/ceh t a = +25c. this data is typical mean test data post radiation exposure at a rate of <10mrad(si)/s. this data is intended to show typical parameter shifts due to low dose rate radiation. these are not limits nor are they guaranteed 0 10 20 30 40 50 60 70 80 90 100 0 255075100125150 krad(si) v hys (mv) biased grounded 120 140 160 180 200 220 240 0 25 50 75 100 125 150 t rst (ms) krad(si) biased grounded 1.0 1.2 1.4 1.6 1.8 2.0 0 25 50 75 100 125 150 t wd (s) krad(si) biased grounded 20 25 30 35 40 0 25 50 75 100 125 150 t md (ns) krad(si) biased grounded 1.000 1.125 1.250 1.375 1.500 0 25 50 75 100 125 150 v pfi (v) krad(si) biased grounded 0 2 4 6 8 10 0 25 50 75 100 125 150 t rpfi (s) krad(si) biased grounded
isl705aeh, isl705beh, isl705ceh, isl706aeh, isl706beh, isl706ceh 11 fn8262.0 march 30, 2012 figure 22. isl705xeh t fpfi vs low dose rate radiation figure 23. isl706xeh i dd vs low dose rate radiation figure 24. isl706xeh v rst vs low dose rate radiation figure 25. isl706xeh v hys vs low dose rate radiation figure 26. isl706xeh t rst vs low dose rate radiation figure 27. isl706xeh t wd vs low dose rate radiation post radiation characteristics unless otherwise specified, v dd = 4.75v to 5.5v for the isl705aeh/beh/ceh, v dd = 3.15v to 3.6v for the isl706aeh/beh/ceh t a = +25c. this data is typical mean test data post radiation exposure at a rate of <10mrad(si)/s. this data is intended to show typical parameter shifts due to low dose rate radiation. these are not limits nor are they guaranteed 0 5 10 15 20 25 30 35 40 0 25 50 75 100 125 150 t fpfi (s) krad(si) biased grounded 300 325 350 375 400 0 25 50 75 100 125 150 krad(si) i dd (a) biased grounded 2.95 3.00 3.05 3.10 3.15 3.20 0 25 50 75 100 125 150 v rst (v) krad(si) biased grounded 0 10 20 30 40 50 60 0 25 50 75 100 125 150 krad(si) v hys (mv) biased grounded 120 140 160 180 200 220 240 0 25 50 75 100 125 150 t rst (ms) krad(si) biased grounded 1.0 1.2 1.4 1.6 1.8 2.0 0 25 50 75 100 125 150 t wd (s) krad(si) biased grounded
isl705aeh, isl705beh, isl705ceh, isl706aeh, isl706beh, isl706ceh 12 fn8262.0 march 30, 2012 figure 28. isl706xeh t md vs low dose rate radiation figure 29. isl706xeh v pfi vs low dose rate radiation figure 30. isl706xeh t rpfi vs low dose rate radiation figure 31. isl706xeh t fpfi vs low dose rate radiation post radiation characteristics unless otherwise specified, v dd = 4.75v to 5.5v for the isl705aeh/beh/ceh, v dd = 3.15v to 3.6v for the isl706aeh/beh/ceh t a = +25c. this data is typical mean test data post radiation exposure at a rate of <10mrad(si)/s. this data is intended to show typical parameter shifts due to low dose rate radiation. these are not limits nor are they guaranteed 20 25 30 35 40 0 25 50 75 100 125 150 t md (ns) krad(si) biased grounded 0.58 0.59 0.60 0.61 0.62 0 25 50 75 100 125 150 v pfi (v) krad(si) biased grounded t rpfi (s) krad(si) 0 5 10 15 20 0 25 50 75 100 125 150 biased grounded 0 5 10 15 20 25 30 35 40 0 25 50 75 100 125 150 t fpfi (s) krad(si) biased grounded
isl705aeh, isl705beh, isl705ceh, isl706aeh, isl706beh, isl706ceh 13 fn8262.0 march 30, 2012 functional overview the isl705xeh and isl706xeh prov ide the functions needed for monitoring critical voltages in hi gh reliability applications, such as microprocessor systems. functions of the these supervisors include power-on reset control, supply voltage supervisions, power-fail detection, manual-reset assert ion and a watch dog timer. the integration of all these functions along with their high threshold accuracy, low power consumption, and radiation tolerance make these devices ideal for critical supply monitoring. reset output reset control has long been a critical aspect of embedded control design. microprocessors require a reset signal during power up to ensure that the syst em environment is stable before initialization. the reset signal provides several benefits: ? it prevents the system microprocessor from starting to operate with insufficient voltage. ? it prevents the processor from operating prior to stabilization of the oscillator. ? it ensures that the monitored de vice is held out of operation until internal registers are initialized. ? it allows time for an fpga to perform its self configuration prior to initialization of the circuit. on power-up, once v dd reaches 1.2v, rst is guaranteed logic low. as v dd rises, rst stays low. when v dd rises above the reset threshold (v rst ), an internal timer releases rst after 200ms (typ). rst pulses low whenever v dd degrades to below v rst (see figure 3). if a brownout condition occurs in the middle of a previously initiated reset pulse, the pulse is lengthened 200ms (typ). on power-down, once v dd falls below the reset threshold, rst stays low and is guaranteed to be low until v dd drops below 1.2v. the isl705beh and isl706beh acti ve-high rst output is simply the complement of the rst output, and is guaranteed to be valid with v dd down to 1.2v. the isl705ceh and isl706ceh active-low open-drain reset output is functionally identical to rst . power failure monitor besides monitoring v dd for reset control, these devices have a power-failure monitor feature that supervises an additional critical voltage on the power-fail input (pfi) pin. for example, the pfi pin could be used to provide an early power-fail warning, overvoltage detection or monitor a power supply other than v dd . pfo goes low whenever pfi is less than v pfi . the threshold detector can be adjusted using an external resistor divider network to provide custom voltage monitoring for voltages greater than v pfi , according to equation 1 (see figure 32). manual reset the manual reset input (mr ) allows designers to add manual system reset capability via a push button switch (see figure 33). the mr input is an active low debounced input that asserts reset if the mr pin is pulled low to less than v il for at least 150ns. after mr is released, the reset output remains asserted for t rst and then released. mr is a ttl/cmos logic compatible, so it can be driven by external logic. by connecting wdo to mr , one can force a watchdog time out to generate a reset pulse. watch dog timer the watchdog time circuit checks for coherent program execution by monitoring the wdi pin. if the processor does not toggle the watchdog input within t wd (1.0s min), wdo will go low. as long as reset is asserted or the wdi pin is tri-stated, the watchdog timer will stay cleared and not count. as soon as reset is released and wdi is driven high or low, the timer will start counting. pulses as short as 50ns can be detected on the isl705xeh, on isl706xeh pulses as short as 100ns can be detected. whenever there is a low-voltage v dd condition, wdo goes low. unlike the reset outputs, however, wdo goes high as soon as v dd rises above its voltage trip po int (see figure 4). with wdi open or connected to a tri-stated high impedance input, the watchdog timer is disabled and only pulls low when v dd < v rst . applications information negative voltage sensing this family of devices can be used to sense and monitor the presence of both a positive and negative rail. v dd is used to monitor the positive supply while pfi monitors the negative rail. pfo is high when the negative rail degrades below a v trip value and remains low when the negative rail is above the v trip value. as the differential voltage across the r1, r2 divider is increased, the resistor values must be chosen such that the pfi node is <1.25v when the -v supply is satisfactory and the positive supply v in v pfi r1 r2 + r2 --------------------- - ?? ?? = (eq. 1) figure 32. custom v th with resistor divider on pfi v in r1 r2 pfi isl705xeh/isl706xeh mr pb 20k figure 33. connecting a manual reset push-button isl705xeh/isl706xeh
isl705aeh, isl705beh, isl705ceh, isl706aeh, isl706beh, isl706ceh 14 fn8262.0 march 30, 2012 is at its maximum specified value. this allows the positive supply to fluctuate within its acceptable range without signaling a reset when configured as shown in figure 34. in figure 34, the isl705aeh is monitoring +5v through v dd and -5v through pfi. in this example, the trip point (v trip ) for the negative supply rail is set for -4.5v. equation 2 can be used to select the appropriate resistor valu es. r1 is selected arbitrarily as 100k ? , v dd = 5v, v pfi = 1.25v, and v trip = (-4.5v). by plugging the values into equation 2 (as shown in equation 3) it can be seen a resistor of 153.3k ? is needed. the closest 1% resistor value is 154k ? . figure 4 also has a general purp ose npn transistor in which the base is connected to the pfo pin through a 100k ? resistor. the emitter is tied to ground and the collector is tied to mr signal. this configuration allows the negative voltage sense circuit to initiate a reset if it is not within its regulation window. a pull-up on the mr ensures no false reset triggering when the negative voltage is within its regulation window. assuring a valid rst output when v dd falls below 1.2v, the rst output can no longer sink current and is essentially an open circuit. as a result, this pin can drift to undetermined voltages if left undriven. by adding a pull-down resistor to the rst pin as shown in figure 35, any stray charge or leakage currents will be drained to ground and keep rst low when v dd falls below 1.2v. the resistor value (r1) is not critical however, it should be large enough not to load rst and small enough to pull rst to ground. a 100k ? resistor would suffice, assuming there is no load on the rst pin during that time. assuring a valid rst output on the isl705beh and isl706beh, when v dd falls below 1.2v, the rst output can no longer sour ce enough current to track v dd . as a result, this pin can drift to undetermined voltages if left undriven. by adding a pull-up resistor to the rst pin as shown in figure 36, rst will track v dd below 1.2v. the resistor value (r1) is not critical however, it should be large enough not to exceed the sink capability of rst pin at 1.2v. a 300k ? resistor would suffice, assuming there is no load on the rst pin during that time. selecting pull-up resistor values the isl705ceh and isl706ceh have open drain active low reset outputs (rst_od ). a pull-up resistor is needed to ensure rst_od is high when v dd is in a valid state (figure 37). the resistor value must be chosen in order not to exceed the sink capability of the rst_od pin. the isl705aeh has a si nk capability of 3.2ma and the isl706ceh has a sink capability of 1.2ma. equation 4 may be used to select resistor r pull based on the pull-up voltage v pull . it is also important that the pull-up voltage does not exceed v dd . figure 34. 5v monitoring r2 r1 v pfi v trip ? () v dd v pfi ? --------------------------------------------- = (eq. 2) r2 100k 1.25 4.5 ? () ? () 51.25 ? ----------------------------------------------------- - 153.3k = = (eq. 3) +5v isl705aeh -5v 100k 100k 2n3904 mr rst pfo pfi r1 r2 v dd figure 35. rst valid to ground circuit figure 36. rst valid to ground circuit figure 37. rst_od pull-up connection isl705aeh, isl706aeh 100k rst v dd isl705beh, isl706beh 300k rst v dd r1 isl706ceh, isl705ceh r pull rst_od v dd v pull
isl705aeh, isl705beh, isl705ceh, isl706aeh, isl706beh, isl706ceh 15 fn8262.0 march 30, 2012 adding hysteresis to the pfi comparator the pfi comparator has no built in hysteresis, however the designer may add hysteresis by connecting a resistor from the pfo pin to the pfi pin, essentially adding positive feedback to the comparator (see figure 38). the following procedure allows the system designer to calculate the components based on the requirements and on given data, such as supply rail voltages , hysteresis band voltage (v hb ), and reference voltage (v pfi ). the comparator only has two states of operation. when it is low, the current through r3 is i r3 = v pfi /r3. when the output is high, i r3 = (v dd - v pfi )/r3. the feedback current needs to be very small so it does not induce oscill ations; 200na is a good starting point. now two values of r3 can be calculated with v dd = 5v and v pfi = 1.25v; r3 = 6.25m ? or 11.25m ? , select the lowest value of the two. with r3 selected as 6.2m ? (closest standard 1% resistor), r1 can be calculated as: with vhb selected at 100mv. the cl osest standard value for r1 is 124k ? . then next step is select the rising trip voltage (vtr) such that: the rising threshold voltage is selected at 3.0v and r2 is calculated by equation 7. plugging in all the variables r2 in this example is 90.9k ? again this is choosing the closest 1% resistor. the final step is verify the trip voltages. the rising voltage, vtr is calc ulated as 2.98v and the falling voltage vtf is calculated as 2.88v so 100mv hysteresis is achieved. an additional item to consider is that the output voltage is equal to v dd , however according to the ?e lectrical specifications? on page 6, the output of the pfi comparator is guaranteed to be at least (v dd -1.5) volts. when you take this worst case into account, the hysteresis can be as low at 70mv. special application considerations using good decoupling practices will prevent transients (i.e., due to switching noises and short duration droops in the supply voltage) from causing unwanted resets and reduce the power-fail circuit?s sensitivity to high-fre quency noise on the line being monitored. when the wdi input is left unconnected, it is recommended to place a 10f capacitor to ground to reduce single event transients from arising in the wdo pin. as described in the ?electrical specifications? table on page 7, there is a delay on the pfo pin whenever pfi crosses the threshold. this delay is due to internal filters on the pfi comparator circuitry which were added to mitigate single event transients. if the pfi input tr ansitions below or above the threshold and the duration of the transition is less than the delay, the pfo pin will not change states. figure 38. positive feedback for hysterisis r pull v pull i sink --------------- - = (eq. 4) isl705aeh rst pfo pfi r1 r2 v dd r3 r1 r3 vhb v dd ----------- ?? ?? 124k = = (eq. 5) vtr v pfi 1 vhb v dd ----------- + ?? ?? > (eq. 6) r2 1 vtr v pfi r1 () ----------------------------- - ?? ?? 1 r1 ------- ?? ?? ? 1 r3 ------- ?? ?? ? ? = (eq. 7) vtr v pfi () r1 1 r1 ------- ?? ?? 1 r2 ------- ?? ?? 1 r3 ------- ?? ?? ++ = (eq. 8) vtf vtr r1 vdd r3 ------------------------- - ?? ?? ? = (eq. 9)
isl705aeh, isl705beh, isl705ceh, isl706aeh, isl706beh, isl706ceh 16 fn8262.0 march 30, 2012 package characteristics weight of packaged device 0.31 grams typical lid characteristics finish: gold lid potential: unbiased case isolation to any lead: 20 x 10 9 ? (min) die characteristics die dimensions 2030m x 2030m (79.9 mils x 79.9 mils) thickness: 483m 25.4m (19.0 mils 1 mil) interface materials glassivation type: silicon oxide and silicon nitride thickness: 0.3m 0.03m to 1.2m 0.12m top metallization type: alcu (99.5%/0.5%) thickness: 2.7m 0.4m backside finish silicon process 0.6m bicmos junction isolated assembly related information substrate potential unbiased additional information worst case current density < 2 x 10 5 a/cm 2 transistor count 1400 metallization mask layout wdo mr vdd gnd pfi pfo wdi rst , rst, rst_od
isl705aeh, isl705beh, isl705ceh, isl706aeh, isl706beh, isl706ceh 17 fn8262.0 march 30, 2012 table 1. die layout x-y coordinates pad name pad number x (m) y (m) dx (m) dy (m) bond wires per pad mr 1 0 01101101 v dd 2 -266.1 -435.35 110 110 1 gnd 3 -266.1 -1184.75 110 110 1 pfi 4 -86.1 -1578 110 110 1 pfo 5 818.85 -1578 110 110 1 wdi 6 1321.9 -1233.5 110 110 1 rst , rst, rst_od 7 1321.9 -534.05 110 110 1 wdo 8 1297 0 110 110 1 note: 8. origin of coordinates is the centroid of pad 1.
isl705aeh, isl705beh, isl705ceh, isl706aeh, isl706beh, isl706ceh 18 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8262.0 march 30, 2012 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change march 30, 2012 fn8262.0 initial release
isl705aeh, isl705beh, isl705ceh, isl706aeh, isl706beh, isl706ceh 19 fn8262.0 march 30, 2012 package outline drawing k8.a 8 lead ceramic metal seal flatpack package rev 2, 12/10 lead finish side view top view -d- -c- 0.265 (6.75) 0.115 (2.92) 0.026 (0.66) 0.265 (6.73) seating and 0.180 (4.57) 0.03 (0.76) min base plane -h- 0.09 (0.23) 0.005 (0.13) pin no. 1 id area 0.050 (1.27 bsc) 0.022 (0.56) 0.015 (0.38) min 0.245 (6.22) 0.070 (1.18) 0.170 (4.32) 0.370 (9.40) 0.250 (6.35) 0.04 (0.10) 0.245 (6.22) 1. adjacent to pin one and shall be loca ted within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. alternately, a tab may be used to identify pin one. 2. of the tab dimension do not apply. 3. the maximum limits of lead dimensions (section a-a) shall be measured at the centroid of the fini shed lead surfaces, when solder dip or tin plate lead finish is applied. 4. 5. shall be molded to the bottom of the package to cover the leads. 6. meniscus) of the lead from the body. dimension minimum shall be reduced by 0.0015 inch (0. 038mm) maximum when solder dip lead finish is applied. 7. 8. notes: 0.015 (0.38) 0.008 (0.20) pin no. 1 id optional 1 2 4 6 3 dimensioning and tolerancing per ansi y14.5m - 1982. controlling dimension: inch. index area: a notch or a pin one identification mark shall be located if a pin one identification mark is used in addition to a tab, the limits measure dimension at all four corners. for bottom-brazed lead packages, no organic or polymeric materials dimension shall be measured at the point of exit (beyond the section a-a base metal 0.007 (0.18) 0.004 (0.10) 0.009 (0.23) 0.004 (0.10) 0.019 (0.48) 0.015 (0.38) 0.0015 (0.04) max 0.022 (0.56) 0.015 (0.38) 0.045 (1.14)

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